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short form data sheet 82P33831 revision 2 12/08/14 1 ?2014 integrated device technology, inc. synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 82P33831 highlights ? synchronization management unit (smu) provides tools to manage physical layer and packet based syn chronous clocks for ieee 1588 / ptp telecom profile applications ? supports independent ieee 1588 and synchronous ethernet (synce) timing paths ? combo mode provides synce phys ical layer frequency support for ieee 1588 telecom boundary clocks (t-bc) and telecom time slave clocks (t-tsc) per g.8273.2 ? digital pll 1 (dpll1) and dpll 2 can be configured as digitally controlled oscillators (dcos) for ptp clock synthesis ? dco frequency resolution is [(77760 / 1638400) * 2^-48] or ~1.686305041e-10 ppm ? dpll1 and dpll2 generate g.8262 compliant synce clocks ? two independent time of day (tod) counters/time accumulators, one associated with each of dpll1 and dpll2, can be used to track dif- ferences between the two time domains and to time-stamp external events ? dpll3 performs rate conversions to frequency synchronization inter- faces or for other general purpose timing applications ? apll3 is voltage controlled crystal oscillator (vcxo) based and generates clocks with jitter <0.3 ps rms (10 khz to 20 mhz) for: 10gbase-r, 10gbase-w and 40gbase-r ? apll1 and apll2 generate clocks with jitter < 1 ps rms (12 khz to 20 mhz) for: 1000base-t and 1000base-x ? fractional-n input dividers suppor t a wide range of reference fre- quencies ? locks to 1 pulse per second (pps) references ? dplls, apll1 and apll2 can be configured from an external eeprom after reset features ? composite clock inputs (in1 and in 2) accept 64 khz synchronization interface signals per itu-t g.703 ? differential reference inputs (in3 to in8) accept clock frequencies between 1 pps and 650 mhz ? single ended inputs (in9 to in14) accept reference clock frequencies between 1 pps and 162.5 mhz ? loss of signal (los) pins (los0 to los3) can be assigned to any clock reference input ? reference monitors qualify/disqua lify references depending on activ- ity, frequency and los pins ? automatic reference selection state machines select the active refer- ence for each dpll based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings ? fractional-n input dividers enable the dplls to lock to a wide range of reference clock frequencies including: 10/100/1000 ethernet, 10g ethernet, otn, sonet/sdh, pdh, tdm, gsm, cpri and gnss frequencies ? any reference input (in3 to in14) can be designated as external sync pulse inputs (1 pps, 2 khz, 4 khz or 8 khz) associated with a select- able reference clock input ? frsync_8k_1pps and mfrsync_2k_1pps output sync pulses that are aligned with the selected external input sync pulse input and frequency locked to the associated reference clock input ? dpll1 and dpll2 can be configured with bandwidths between 0.09 mhz and 567 hz ? dpll1 and dpll2 lock to input references with frequencies between 1 pps and 650 mhz ? dpll3 locks to input references with frequencies between 8 khz and 650 mhz ? dpll1 and dpll2 comply with itu-t g.8262 for synchronous ethernet equipment clock (eec), and g.813 for synchronous equip- ment clock (sec); and telcordi a gr-253-core for stratum 3 and sonet minimum clock (smc) ? dpll1 and dpll2 generate clocks with pdh, tdm, gsm, cpri/ obsai, 10/100/1000 ethernet and gnss frequencies; these clocks are directly available on out1 ? dpll1 and dpll2 can be configured as dcos to synthesize ieee 1588 clocks ? dpll3 generates n x 8 khz clocks up to 100 mhz that are output on out9 and out10 ? apll1, apll2 and apll3 can be connected to dpll1 or dpll2 ? apll1 and apll2 generate 10/100/1000 ethernet, 10g ethernet, or sonet/sdh frequencies ? apll3 generates 10g ethernet, wan-phy and lan-phy frequen- cies ? any of eight common tcxo/ocxo frequencies can be used for the system clock: 10 mhz, 12.8 mhz, 13 mhz, 19.44 mhz, 20 mhz, 24.576 mhz, 25 mhz or 30.72 mhz ? the i2c slave interface can be used by a host processor to access the control and status registers ? the i2c master interface can aut omatically load a device configura- tion from an external eeprom after reset; apll3 must be config- ured via the i2c slave interface ? dpll1 or dpll3 can be connected to an internal composite clock generator that outputs its 64 khz synchronization signal on out8 ? differential outputs out3 to out6 output clocks with frequencies between 1 pps and 650 mhz ? differential outputs out11 and out12 output clocks with frequen- cies up to 650 mhz ? single ended outputs out1, out2 and out7 output clocks with fre- quencies between 1 pps and 125 mhz ? single ended outputs out9 and out10 output clocks n*8khz multi- ples up to 100 mhz ? dpll1 and dpll2 support independent programmable delays for each of in3 to in14; the delay for each input is programmable in steps of 0.61 ns with a range of ~78 ns
82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 2 revision 2 12/08/14 ? the input to output phase delay of dpll1 and dpll2 is program- mable in steps of 0.0745 ps with a total range of 20 s ? the clock phase of each of the output dividers for out1 (from apll1) to out7 is individually programmable in steps of ~200 ps with a total range of +/-180 ? 1149.1 jtag boundary scan ? 144-pin cabga green package applications ? access routers, edge routers, core routers ? carrier ethernet switches ? multiservice access platforms ? pon olt ? lte enodeb ? ieee 1588 / ptp telecom profile clock synthesizer ? itu-t g.8273.2 telecom boundary clock (t-bc) and telecom time slave clock (t-tsc) ? itu-t g.8264 synchronous equipment timing source (sets) ? itu-t g.8263 packet-based equipment clock (pec) ? itu-t g.8262 synchronous ethernet equipment clock (eec) ? itu-t g.813 synchronous equipment clock (sec) ? telcordia gr-253-core stratum 3 clock (s3) and sonet mini- mum clock (smc) description the 82P33831 synchronization management unit (smu) provides tool s to manage timing references, cl ock sources and timing paths f or ieee 1588 / precision time protocol (ptp) and synchronous ethernet (synce) based clocks. the device supports up to three independent timing paths that control: ptp clock synthesis; sy nce clock generation; and general purpose fr equency translation. the device supports physi cal layer timing with digital plls (dplls) and it supports packet based timing with digitally controlled o scillators (dcos). input-to- input, input-t o-output and output-to- output phase skew can all be precisely managed. the device outputs lo w-jitter clocks that can directly synchronize 40gbase-r, 1 0gbase-r and 10gbase-w and lower-rate ethernet interfaces; as well as cpri/obsai, sonet/sdh and pdh interfaces and ieee 1588 time stamp unit s (tsus). the 82P33831 accepts six differential reference inputs and six si ngle ended reference inputs that can operate at common gnss, e thernet, sonet/sdh and pdh frequencies that range in frequency from 1 pulse per second (pps) to 650 mhz. the device also provides two al ternate mark inversion (ami) inputs for composite clock (cc) signals bearing 64 khz, 8 khz and 0.4 khz synchr onization information. the refe rences are continu- ally monitored for loss of signal and for frequency offset per user programmed thresholds. all of the references are available to all three dplls. the active reference for each dpll is determined by forced selecti on or by automatic selection bas ed on user programmed priorities and locking allow- ances and based on the reference monitors and los inputs. the 82P33831 can accept a clock reference and an associated phase locked sync signal as a pair. dpll1 or dpll2 can lock to the clock refer- ence and align the frame sync and multi-frame sy nc outputs with the paired sync input. t he device allows any of the differentia l or single ended refer- ence inputs to be configured as sync inputs that can be associat ed with any of the other diff erential or single ended reference inputs. the input sync signals can have a frequency of 1 pps, 2 khz, 4 khz or 8 khz. th is feature enables dpll1 or dpll2 to phase align its frame sync and multi-frame sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input. dpll1 and dpll2 support four primary operating m odes: free-run, locked, holdover and dco. in free-run mode the dplls synthesize clocks based on the system clock alone. in locked mode the dplls filter reference clock jitter with t he selected bandwidth. in locked mode, the long-term output frequency accuracy is the same as the long term frequency accu racy of the selected input reference. in holdover mode, th e dpll uses fre- quency data acquired while in locked mode to generate accurate freque ncies when input references ar e not available. in dco mode the dpll con- trol loop is opened and the dco can be controlled by a ptp clock re covery servo running on an exter nal processor to synthesize ptp clocks. the 82P33831 requires a system clock for it s reference monitors and other digital ci rcuitry. the frequency accuracy of the syst em clock deter- mines the frequency accuracy of the dplls in free-run mode. the frequency stability of the system clock determines the frequenc y stability of the dplls in free-run mode and in holdover mode; and it affect s the wander generation of the dplls in locked and dco modes. when used with a suitable system clock, dpll1 and dpll2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generati on, noise toler- ance, transient response, and holdover per formance requirements of the following applications: itu-t g.8262/g.813 eec/sec optio ns 1 and 2, itu- t g.8263, itu-t g.8273.2, telcordia gr-1244 stratum 3 (s3), telcor dia gr-253-core stratum 3 (s3) and sonet minimum clock (smc). dpll1 and dpll2 can be configured with a range of selectable filt ering bandwidths from 0.09 mhz to 567 hz. the 17 mhz bandwidth can be used to lock the dpll directly to a 1 pps reference. the 69 mhz and the 92 mhz bandwidths can be used for g.8273.2. the 92 mhz bandwidth can be used for g.8262/g.813 option 2 or telcordia gr-253-core s3 or smc applications. the bandwidths in the range 1.1 hz to 8.9 hz can be used for g.8262/g.813 option 1 applications. bandwidths above 10 hz can be used in jitter attenuation and rate conversion applicatio ns. dpll1 and dpll2 are each connected to time of day (tod) counters or time accumulators; these tod counters/time accumulators can be used to track differences between the two time domains and to time-stamp external event s by using reference inputs as triggers. dpll3 supports three primary operation modes: free-run, lock ed and holdover. dpll3 is a wideband (bw > 25hz) frequency translat or that can be used, for example, to convert a recovered line clock to a 1.544 mhz or 2.048 mhz synchr onization interface clock.
82P33831 short form data sheet revision 2 12/08/14 3 synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet in telecom boundary clock (t-bc) and telecom time slave clock (t-tsc) applications per itu-t g.8275.2, dpll1 and dpll2 are both used; one dpll is configured as a dco to synthesize ptp clocks and the other dpll is configured as an eec/sec to generate physical la yer clocks. combo mode provides physical layer frequency s upport from the eec/sec to the ptp clock. in synchronous equipment timing source ( sets) applications per itu-t g.8264, dpll1 or dpll2 can be configured as an eec/sec to output clocks for the t0 reference point and dpll3 can be us ed to output clocks for the t4 reference point. clocks generated by dpll1 or dpll2 can be pas sed through apll1 or apll2 which are lc bas ed jitter attenuating analog plls (apll s). the output clocks generated by apll1 and apll2 are suitabl e for serial gbe and lower rate interfaces. clocks generated by dpll1 or dpll2 can be passed through apll3 which is a voltage controlled crystal oscillator (vcxo) based ji tter attenuat- ing apll. apll3 can be provisioned with one or two selectable crystal resonators to support up to two base frequencies. the out put clocks gener- ated by apll3 are suitable for serial 40gbase-r and lower rate interfaces. the device provides an ami output for a cc signal bearing 64 khz, 8 khz and 0.4 khz sync hronization information. the cc output can be con- nected to either dpll1 or dpll3. all 82P33831 control and status registers are accessed through an i2c slave microprocesso r interface. for configuring the dplls , apll1 and apll2, the i2c master interface can automatically load a configur ation from an external eeprom after reset. apll3 must be confi gured via the i2c slave interface.
82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 4 revision 2 12/08/14 functional block diagram figure 1. functional block diagram control and status registers outdiv outdiv i2c slave jtag i2c master reference monitors reference selection frac-n input dividers sys pll dpll2 / dco2 apll1 apll2 outdiv outdiv outdiv dpll1 / dco1 out3p/n out4p/n out5p/n out6p/n out7 system clock los0 / xo_freq0 los1 / xo_freq1 los2 / xo_freq2 los3 ex_sync module composite clocks in1(cc) in2(cc) in5(p/n) in6(p/n) in7(p/n) in3(p/n) in4(p/n) in8(p/n) in9 in10 in11 in12 in13 in14 frsync_8k_1pps mfrsync_2k_1pps crystal outdiv out1 outdiv out2 outdiv outdiv out11p/n out12p/n apll3 (vcxo) outdiv outdiv out9 out10 out8 composite clock dpll3 tod/ time accumulator tod/ time accumulator
82P33831 short form data sheet revision 2 12/08/14 5 synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 1 pin assignment figure 1. pin assignment (top view) 123456789101112 a out5_pos out5_neg out6_pos out6_neg vddao out12_pos vddao out11_pos cap2 xtal2_in sonet/sdh/lo s3 xtal1_in a b vssao vddao vddao vssao vssao out12_neg vssao out11_neg vssa xtal2_out mpu_mode1/i 2cm_scl xtal1_out b c vdda vssa vss out7 i2c_sda vdda vdda ic cap1 ic mpu_mode0/i 2cm_sda mfrsync_2 k_1pps c d vssa vdda vsscom vssd vddd vssa vssa cap3 i2c_ad2 i2c_scl out10 out9 d e osci vssa ic vdddo i2c_ad1 vddd0 vssdo vssa dpll3_lock in14 in13 frsync_8k_ 1pps e f tms vdda vssa vssdo vss vssd vddd vssa vdda in12 in8_neg in8_pos f g tck vdda ic vss vss vss ic vss dpll2_lock in11 in7_neg in7_pos g h xo_freq0/ los0 vdda vssa vss vss vss vss vss dpll1_lock in10 vssd vddd_1_8 h j xo_freq1/ los1 xo_freq2/ los2 vss vss vss vss vss vss int_req in9 in6_neg in6_pos j k vdda vdda trstb vssao out2 rstb vssdo ms_sl in2 in1 in5_neg in5_pos k l vssa vssa tdi vddao tdo ic vdddo out1 vssd vddd_1_8 in4_neg in4_pos l m out4_pos out4_neg vssao vddao out3_pos out3_neg vssdo vdddo out8_pos out8_neg in3_neg in3_pos m 123456789101112
82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 6 revision 2 12/08/14 1 pin description table 1: pin description pin no. name i/o type description global control signal e1 osci i cmos osci: crystal oscillator system clock a clock provided by a crystal oscillator is input on this pin. it is the system clock for the device. the oscillator frequency is selected via pins xo_freq0 ~ xo_freq2. k8 ms/sl i pull-up cmos ms/sl: master / slave selection this pin, together with the ms_sl_ctrl bit, controls whether the device is configured as the master or as the slave. the signal level on this pin is reflected by the master_slave bit. a11 sonet/sdh/ los3 i pull-down cmos sonet/sdh: sonet / sdh frequency selection during reset, this pin determines the default value of the in_sonet_sdh bit (b2, 09h): high: the default value of the in_sonet_sdh bit is ?1? (sonet); low: the default value of the in_sonet_sdh bit is ?0? (sdh). after reset, this pin takes on the operation of los3. los3- this pin is used to disqualify input clocks. see input clocks section for more details. k6 rstb i pull-up cmos rstb: reset a low pulse of at least 50 s on this pin re sets the device . if loading from an eeprom, the maximum time from rstb de-assert to have stable clocks is 100ms. if not loading from eeprom the maximum time from rstb de-a ssert to have stab le clocks is 5ms. h1 j1 j2 xo_freq0/ los0 xo_freq1/ los1 xo_freq2/ los2 i pull-down cmos xo_freq0 ~ xo_freq2: these pins set the oscillator frequency. xo_freq[2:0] oscillator frequency (mhz) 000 10.000 001 12.800 010 13.000 011 19.440 100 20.000 101 24.576 110 25.000 111 30.720 los0 ~ los2 - these pins are used to disqualify input clocks. see input clocks section for more details. after reset, these pins take on the operation of los0-2. input clock and frame synchronization input signal k10 in1 i ami in1: input clock 1 a 64 khz + 8 khz or 64 khz + 8 khz + 0.4 khz composite clock is input on this pin. ami input has internal 1k ohm to 1.5v termination. this pin can also be used as a frame pulse input, and in this case an 8 khz signal can be input on this pin. k9 in2 i ami in2: input clock 2 a 64 khz + 8 khz or 64 khz + 8 khz + 0.4 khz composite clock is input on this pin. ami input has internal 1k ohm to 1.5v termination. this pin can also be used as a frame pulse input, and in this case an 8 khz signal can be input on this pin. m12 m11 in3_pos in3_neg i pecl/lvds in3_pos / in3_neg: positive / negative input clock 3 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. l12 l11 in4_pos in4_neg i pecl/lvds in4_pos / in4_neg: positive / negative input clock 4 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. k12 k11 in5_pos in5_neg i pecl/lvds in5_pos / in5_neg: positive / negative input clock 5 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. j12 j11 in6_pos in6_neg i pecl/lvds in6_pos / in6_neg: positive / negative input clock 6 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. g12 g11 in7_pos in7_neg i pecl/lvds in7_pos / in7_neg: positive / negative input clock 7 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin.
82P33831 short form data sheet revision 2 12/08/14 7 synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet f12 f11 in8_pos in8_neg i pecl/lvds in8_pos / in8_neg: positive / negative input clock 8 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. j10 in9 i pull-down cmos in9: input clock 9 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. h10 in10 i pull-down cmos in10: input clock 10 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. g10 in11 i pull-down cmos in11: input clock 11 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. f10 in12 i pull-down cmos in12: input clock 12 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. e11 in13 i pull-down cmos in13: input clock 13 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. e10 in14 i pull-down cmos in14: input clock 14 a reference clock is input on this pin. this pin can also be used as a sync input, and in this case a 2 khz, 4 khz, 8 khz, or 1pps signal can be input on this pin. output frame synchronization signal e12 frsync _8k_1pps ocmos frsync_8k_1pps: 8 khz frame sync output an 8 khz signal or a 1pps sync signal is output on this pin. c12 mfrsync _2k_1pps ocmos mfrsync_2k_1pps: 2 khz mu ltiframe sync output a 2 khz signal or a 1pps sync signal is output on this pin. output clock l8 k5 out1 out2 ocmos out1 ~ out2: output clock 1 ~ 2 m5 m6 out3_pos out3_neg o pecl/lvds out3_pos / out3_neg: positive / negative output clock 3 this output is set to lvds by default. the lvds output has internal 100 ohm termination. m1 m2 out4_pos out4_neg o pecl/lvds out4_pos / out4_neg: positive / negative output clock 4 this output is set to lvds by default. the lvds output has internal 100 ohm termination. a1 a2 out5_pos out5_neg o pecl/lvds out5_pos / out5_neg: positive / negative output clock 5 this output is set to lvds by default. the lvds output has internal 100 ohm termination. a3 a4 out6_pos out6_neg o pecl/lvds out6_pos / out6_neg: positive / negative output clock 6 this output is set to lvds by default. the lvds output has internal 100 ohm termination. c4 out7 o cmos out7: output clock 7 m9 m10 out8_pos out8_neg oami out8_pos / out8_neg: positive / negative output composite clock a 64 khz + 8 khz or 64 khz + 8 khz + 0.4 khz composite clock is differentially output on this pair of pins. d12 out9 o cmos out9: output clock 9 d11 out10 o cmos out10: output clock 10 a8 b8 out11_pos out11_neg o pecl out11_pos / out11_neg: positive / negative output clock 11 a6 b6 out12_pos out12_neg o pecl out12_pos / out12_neg: positive / negative output clock 12 table 1: pin description (continued) pin no. name i/o type description
82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 8 revision 2 12/08/14 miscellaneous c9, a9, d8 cap1, cap2, cap3 cap1, cap2 and cap3: analog power filter capacitor connection 1 to 3. these capacitors are be part of the power filtering. a12 xtal1_in i analog crystal oscillator 1 input. determines first of two frequency families (sonet/sdh, ethernet or ethernet*66/64) available for apll3. connect to ground if xtal1 is not used. b12 xtal1_out o analog crystal oscillator 1 output. leave open if xtal1 is not used. a10 xtal2_in i analog crystal oscillator 2 input. determines first of two frequency families (chosen from sonet/sdh, ethernet or ethernet*66/ 64) available for apll3. connect to ground if xtal2 is not used b10 xtal2_out o analog crystal oscillator 2 output. leave open if xtal2 is not used. lock signal e9 dpll3_lock ocmos dpll3_lock this pin goes high when dpll3 is locked g9 dpll2_lock ocmos dpll2_lock this pin goes high when dpll2 is locked h9 dpll1_lock ocmos dpll1_lock this pin goes high when dpll1 is locked microprocessor interface j9 int_req o tri-state cmos int_req: interrupt request this pin is used as an interrupt request. b11 c11 mpu_mode1/ i2cm_scl mpu_mode0/ i2cm_sda i/o pull-down cmos/ open drain mpu_mode[1:0]: microprocessor interface mode selection during reset, these pins determine the default value of the mpu_sel_cnfg[1:0] bits as fol- lows: 00: i2c mode 01 ~ 10: reserved 11: i2c master (eeprom) mode i2cm_scl : serial clock line in i2c master mode, the serial clock is output on this pin. i2cm_sda : serial data input for i2c master mode in i2c master mode, this pin is used as the for the serial data. d9 i2c_ad2 i pull-down cmos i2c_ad2: device address bit 2 i2c_ad[2:1] pins are the address bus of the microprocessor interface. e5 i2c_ad1 i pull-down cmos i2c_ad1: device address bit 1 i2c_ad[2:1] pins are the address bus of the microprocessor interface. d10 i2c_scl i cmos i2c_scl: serial clock line the serial clock is input on this pin. c5 i2c_sda i/o open drain i2c_sda: serial data input/output this pin is used as the input/output for the serial data. jtag (per ieee 1149.1) f1 tms i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. k3 trstb i pull-down cmos trstb: jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. table 1: pin description (continued) pin no. name i/o type description
82P33831 short form data sheet revision 2 12/08/14 9 synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 1.1 recommendations for unused input and output pins 1.1.1 inputs control pins all control pins have internal pul l-ups or pull-downs ; additional resis- tance is not required but can be added for additional protection. a 1k resistor can be used. single-ended clock inputs for protection, unused single- ended clock inputs should be tied to ground. differential clock inputs for applications not requiring the use of a differential input, both *_pos and *_neg can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _pos to ground. xtal inputs for applications not requiring the use of a crystal oscillator input, both _in and _out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _in to ground. 1.1.2 outputs status pins for applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. single-ended clock outputs all unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. differential clock outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. g1 tck i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. l3 tdi i pull-up cmos tdi: jtag test data input the test data are input on this pin. they are clocked into the device on the rising edge of tck. l5 tdo o tri-state cmos tdo: jtag test data output the test data are output on this pin. they are clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. power & ground c1, c6, c7, d2, f2, f9, g2, h2, k1, k2 vdda power - vdda : analog core power - +3.3v dc nominal a5, a7, b2, b3, l4, m4 vddao power vddao : analog output power - +3.3v dc nominal e4, e6, l7, m8 vdddo power vdddo : digital output power - +3.3v dc nominal d5, f7 vddd power vddd : digital core power - +3.3v dc nominal l10, h12 vddd_1_8 power vddd_1_8 : digital core power - +1.8v dc nominal b9, c2, d1, d6, d7, e2, e8, f3, f8, h3, l1, l2 vssa ground - vssa : ground b1, b4, b5, b7, k4, m3 vssao ground vssao : ground e7, f4, k7, m7 vssdo ground vssdo : ground d4, f6, h11, l9 vssd ground vssd : ground d3 vsscom ground - vsscom: ground c3, f5, g4, g5, g6, g8, h4, h5, h6, h7, h8, j3, j4, j5, j6, j7, j8 vss ground - vss : ground other c8, c10, e3, g3, g7, l6 ic - - ic : internal connection internal use. this pin must be left open for normal operation. table 1: pin description (continued) pin no. name i/o type description
idt82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 10 revision 2 12/08/14 package dimensions figure 1. 144-pin bag package dimensions
idt82P33831 short form data sheet revision 2 12/08/14 11 synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet figure 2. 144-pin bag package recommended land pattern
idt82P33831 short form data sheet synchronization management unit for ieee 1588 and 10g/40g synchronous ethernet 12 revision 2 12/08/14 ordering information "g" after the two-letter package code denotes pb-free configuration, rohs compliant. table 1: ordering information part/order number package temperature 82P33831abag 144-pin cabga green package -40 o to +85 o c
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